About ACM - IEEE CS Eckert-Mauchly

ACM and IEEE Computer Society named Srinivas Devadas as the recipient of the 2026 ACM-IEEE CS Eckert-Mauchly Award. Devadas, the Webster Professor of Electrical Engineering and Computer Science (EECS) at the Massachusetts Institute of Technology, is cited for pioneering contributions to secure architectures with broad industrial and academic impact

Devadas pioneered the field of hardware security at a time when it was considered by many to be a niche or even fanciful pursuit. However, in the last 25 years, with the advent of smart phones and cloud computing, the majority of information is now stored in the computing infrastructure. Hardware security has become a fundamental design principle in computer architecture with most design groups now maintaining dedicated teams focused on security. Devadas coupled foundational research with a range of practical and widely adopted defenses that have shaped both academia and industry.

Devadas made foundational contributions in three main areas: Trusted Execution Environments (TEEs), Physical Unclonable Functions (PUFs), and Side Channel Resistant Processors. These innovations have touched the lives of billions of people by safeguarding their data in a digital world

In 2003, Devadas’ group at MIT introduced AEGIS, a new single-chip secure processor which incorporates mechanisms to authenticate the platform and software, as well as mechanisms to protect applications from physical and software attacks. AEGIS was the first demonstration of a single-chip processor providing cryptographically-attested Trusted Execution Environments (TEEs). This innovation was revolutionary at the time because it allowed programs to run securely even when the privileged operating system or external memory was completely compromised. TEEs were ahead of their time in protecting computers from a wide range of threats including operating systems, IT Staff, and untrusted software. TEEs are now used broadly to protect sensitive information and data in the cloud.

Secure computing requires secret keys, typically stored in physically-insecure, non-volatile memory. Devadas realized that manufacturing variation can be used to generate secret keys and invented Physical Unclonable Functions (PUFs). PUFs generate highly secure keys which only exist when the chip is powered. They are widely used now in leading commercial products including; Xilinx and Intel field programmable gate arrays (FPGAs), Samsung’s Exynos processors, and many other cryptoprocessors (e.g., Maxim, Microsemi).

Software side-channel attacks including cache timing and Spectre attacks can circumvent TEE protections. In response, Devadas’ group developed new secure processors (Sanctum, MI6, and Ascend) that can withstand side-channel attacks. Crucially, his group proposed a security-monitor-based architecture that minimally impacts hardware, which has inspired RISC-V enclaves and the first asymptotically-optimal, Oblivious Random Access Memory (ORAM) algorithm Path ORAM, which blocks memory access pattern attacks. Path ORAM is used with Intel SGX in the popular Signal messaging app.

After more than 37 years in the field, Devadas continues to be at the forefront of modern cryptography and its impact on hardware. He is also preparing the next generation of researchers for the challenges ahead in secure computer architecture.

ACM and IEEE Computer Society named André Seznec as the recipient of the ACM-IEEE CS Eckert-Mauchly Award. Seznec, a Fellow Research Director at INRIA/IRISA and a Fellow at SiFive, is recognized for his extensive impact on computing, most notably pioneering contributions to branch prediction and cache memories. 

Seznec’s inventions can be found in billions of CPUs worldwide. These include the TAGE branch predictor and skewed-associative cache. In fact, Seznec’s work has served as a gold standard of branch prediction for the last 15 years, with most current structures in industrial designs rooted in his trailblazing contributions.

His early contributions were in vector architectures, particularly the memory system. Since the early 1990s, his main research activity has been focused on the architecture of microprocessors, including caches, pipelines, branch predictors, speculative execution, multithreading, and multicores. His research has influenced the design of many high-end industrial microprocessors, particularly the caches and the branch predictors.

Over the course of his career, Seznec has published more than 100 papers with many of his most notable contributions published solely under his name, demonstrating the profound impact he has had in solving some of the most challenging problems in computer architecture.

In addition, Seznec has been a dedicated supporter of industry education, collaboration, and advancement. He served multiple years on the organizing committee of the IEEE/ACM International Symposium on Computer Architecture (ISCA) acting as general chair in 2010 and program committee chair in 2016. He has also supported the future of computing as an educator, having graduated 28 PhD students from 1991 to 2020.

ACM and IEEE Computer Society named Wen-mei W. Hwu, a Senior Distinguished Research Scientist at NVIDIA and Professor Emeritus at the University of Illinois, Urbana-Champaign, the recipient of the ACM-IEEE CS Eckert-Mauchly Award. Hwu is recognized for pioneering and foundational contributions to the design and adoption of multiple generations of processor architectures. His fundamental and pioneering contributions have had a broad impact on three generations of processor architectures: superscalar, VLIW, and throughput-oriented manycore processors (GPUs).

Hwu was one of the original architects of the High-Performance Substrate (HPS) model that pioneered superscalar microarchitecture, introducing the concepts of dynamic scheduling, branch prediction, speculative execution, a post-decode cache, and in-order retirement. He co-authored the two original 1985 HPS papers, “Critical Issues Regarding HPS, a High Performance Microarchitecture” and “HPS, A New Microarchitecture: Rationale and Introduction,” both of which received the inaugural MICRO Test-of-Time Award in 2014.

By 1987, the rapid increase in hardware execution resources created pressing needs for instruction-level parallelizing compilers. Hwu addressed the problem by constructing a revolutionary compiler infrastructure in his paper, “IMPACT: An Architectural Framework for Multiple-Instruction Issue,” which demonstrated compilers can generate code with far more parallelism than most researchers thought possible. This paper also pioneered architecture support for control speculation and received the 2006 ISCA Most Influential Paper Award.

For his work on architecture support for ILP compilers, he received ACM SIGARCH’s first Maurice Wilkes award in 1998. He published foundational papers on superblock and hyperblock structures. The superblock is a pervasive compiler technique, adopted by major vendor compilers and the GNU C Compiler. In academia, the hyperblock work influenced many projects, most notably the TRIPS project at the University of Texas. In 1999, Hwu received the ACM Grace M. Hopper Award “for the design and implementation of the IMPACT compiler.”

Since 2006, Hwu has focused on designing and deploying throughput-oriented heterogeneous parallel computing architectures. His team pioneered the programmer optimization principles in their PPoPP 2008 paper and the Pareto-optimal pruning of search space for auto-tuning in their CGO 2008 paper for GPUs. The CGO 2008 paper won the 2018 CGO Test-of-Time Award  These works not only enabled wide adoption of CUDA-enabled GPUs but also helped the NVIDIA architecture team to improve the programmability of several generations of GPUs. The four editions of the textbook by Hwu and David Kirk (former Chief Scientist of NVIDIA), Programming Massively Parallel Processors, have sold more than 25,000 copies and the book has been translated into five languages.

Hwu’s contributions to education also include three offerings of the Coursera course on Heterogeneous Parallel Programming that were attended by more than 20,000 students, with 5,000 completing all exams and quizzes to receive a certificate. Hwu and Kirk are widely credited for their contributions in making the GPU the computing device of choice for the HPC/ML communities. Hwu’s architecture and compiler techniques have impacted billions of processors.

Hwu will be formally recognized with the Eckert-Mauchly Award during an awards luncheon on Tuesday, July 2, at the International Symposium on Computer Architecture (ISCA 2024 ).

ACM and IEEE Computer Society named Kunle Olukotun, a Professor at Stanford University, as the recipient of the ACM-IEEE CS Eckert-Mauchly Award for contributions and leadership in the development of parallel systems, especially multicore and multithreaded processors.

In the early 1990s, Olukotun became a leading designer of a new kind of microprocessor known as a "chip multiprocessor"—today called a "multicore processor." His work demonstrated the performance advantages of multicore processors over the existing microprocessor designs at the time. He included these ideas in a landmark paper presented at the ACM Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 1996), entitled "The Case for a Single-Chip Multiprocessor." This paper received the ASPLOS Most Influential Paper Award 15 years later. Olukotun’s multicore design eventually became the industry standard.

His insights on multicore processors and thread-level speculation research laid the foundation for Olukotun's work on fine-grained multithreading, a technique which improves the overall efficiency of computer processors (CPUs). These designs were the basis for Afara WebSystems, a server company Olukotun founded that was eventually acquired by Sun (and later Oracle). Sun Microsystems used Olukotun’s designs as a foundation for its Niagara chips, which were recognized for their outstanding performance and energy efficiency. The Niagara family of chips are now used in all of Oracle's SPARC-based servers.

Later, with Christos Kozyrakis and others, Olukotun was a leader in designing the Transactional Coherence and Consistency (TCC) approach to simplify parallel programming. He was a co-author of the paper, “Transactional Memory Coherence and Consistency,” which was presented at the 2004 International Symposium on Computer Architecture (ISCA) and received the Most Influential Paper Award in 2019. Olukotun is one of only two researchers who have received the Most Influential Paper Award from both ASPLOS and ISCA.

ACM and IEEE Computer Society co-sponsor the Eckert-Mauchly Award, which was initiated in 1979. It recognizes contributions to computer and digital systems architecture and comes with a $5,000 prize. The award was named for John Presper Eckert and John William Mauchly, who collaborated on the design and construction of the Electronic Numerical Integrator and Computer (ENIAC), the pioneering large-scale electronic computing machine, which was completed in 1947.

He will be formally recognized with the Eckert-Mauchly Award during an awards luncheon on Tuesday, June 20th at the International Symposium on Computer Architecture (ISCA 2023).

ACM and IEEE Computer Society named Mark Horowitz, a Professor at Stanford University, as the recipient of the 2022 Eckert-Mauchly Award for contributions to microprocessor memory systems. Horowitz was the first to identify the processor to dynamic random-access memory (DRAM) interface as a key bottleneck that required architecture and circuit optimization. He pioneered high-bandwidth DRAM interfaces. In addition, modern DRAM interfaces such as SDDR and LPDDR were strongly influenced by his techniques.

Horowitz was also a major contributor to the DASH and FLASH projects, which explored scalable methods for implementing cache coherency using directories rather than snooping protocols. Today almost all cache-coherent multiprocessors rely on such directory mechanisms either within or across multicores. Horowitz has led research that recognizes that future performance/energy progress after the end of Dennard scaling will require greater use of hardware accelerators, and pioneered work in Smart Memories, an early work customizing memory as well as processors; many of today’s domain-specific architectures build on this concept. He is a Fellow of ACM, IEEE, and the American Academy of Arts and Sciences, and he is a Member of the National Academy of Engineering.

Horowitz will be formally presented with the award at the ACM/IEEE International Symposium on Computer Architecture (ISCA) being held June 18–22 in New York City.

ACM and IEEE Computer Society co-sponsor the Eckert-Mauchly Award, which was initiated in 1979. It recognizes contributions to computer and digital systems architecture and comes with a $5,000 prize. The award was named for John Presper Eckert and John William Mauchly, who collaborated on the design and construction of the Electronic Numerical Integrator and Computer (ENIAC), the pioneering large-scale electronic computing machine, which was completed in 1947.

ACM and IEEE Computer Society named Margaret Martonosi, the Hugh Trumbull Adams '35 Professor of Computer Science at Princeton University, as the recipient of the 2021 Eckert-Mauchly Award for contributions to the design, modeling, and verification of power-efficient computer architecture.

Martonosi has made significant contributions in computer architecture and microarchitecture, and her work has led to new fields of research. She has authored more than 175 publications (with 17,000 + citations) on subjects including parallel architectures, memory hierarchies, compilers, and mobile networks.

Power/Thermal Aware Architectures
Martonosi was an early innovator in the design and modeling of power-aware microarchitectures, including using narrow bit-widths, modeling and responding to thermal issues, and performing power estimation, e.g., as embodied in the ubiquitous Wattch tool.

In the area of narrow bit-widths, Martonosi co-authored (with David Brooks) the paper “Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance.” Martonosi and Brooks introduced two optimizations which greatly reduced processor power consumption. The paper earned the HPCA Test of Time Award and the optimizations were licensed to Intel. Martonosi developed subsequent microarchitectural proposals that expanded on this work.

In a later (2001) paper with David Brooks “Dynamic Thermal Management for High-Performance Microprocessors,” Martonosi investigated dynamic thermal management as a technique to control CPU power dissipation. Martonosi and Brooks demonstrated that, with appropriate thermal management, a CPU can be designed for a much lower maximum power rating, with minimal performance impact for typical applications. This was the first computer architecture paper to explicitly focus on thermal issues.

In a series of papers, Martonosi was also the first researcher to demonstrate how to use formal control-theoretic approaches to balance power and performance for dynamic voltage and frequency scaling (DVFS).

Power Simulation and Estimation
Martonosi recognized early the need for microarchitecture- and architecture-level power modeling and measurement infrastructure. She was a co-developer (with David Brooks and Vivek Tiwari) of Wattch, an architectural simulator that estimates CPU power consumption, which is used by thousands of researchers today. Wattch broke ground by demonstrating (against conventional wisdom) that accurate early-stage power models could be developed for early-stage microarchitectural design tradeoffs before more detailed computer-aided design (CAD) tools can be used. Martonosi also developed live runtime measurement tools for detailed power assessments of widely used and complex microprocessor systems.

ZebraNet Full-Stack Computing Platform
Martonosi broadened her scope beyond conventional computers to energy issues in mobile sensor networks, where energy fundamentally dictates system lifetime and data-gathering success.

Martonosi’s ZebraNet Wildlife Tracking Project established the new research field of Mobile Sensor Networks. ZebraNet collected thousands of data points on Plains Zebras in Kenya. ZebraNet developed energy-efficient protocols for short-range, pairwise data transfers. Martonosi’s work demonstrated that sparsely deployed mobile sensors could offer high data delivery rates and sensor coverage over large areas, at practical power budgets. ZebraNet provided biologists with never-before-seen animal behavior data. The work resulted in two test-of-time awards and several widely cited papers.

Memory Consistency Model Specification and Verification
Martonosi’s groundbreaking work has demonstrated the potential of fast, early-stage formal methods to verify the correctness of memory consistency model implementation. This work, embodied in the Check suite of verification tools, has had immediate and significant impact.

Modern hardware complexity also presents security challenges, and the Check suite includes efforts to provide rigorous and automated approaches for determining if a microarchitecture is susceptible to specified classes of security exploits. This kind of automatic checking will be fundamental to future information security.

Martonosi will be formally recognized with the ACM-IEEE CS Eckert-Mauchly Award during the ACM/IEEE International Symposium on Computer Architecture (ISCA), which is being held virtually this year from June 14-19.

ACM and IEEE Computer Society co-sponsor the Eckert-Mauchly Award, which was initiated in 1979. It recognizes contributions to computer and digital systems architecture and comes with a $5,000 prize. The award was named for John Presper Eckert and John William Mauchly, who collaborated on the design and construction of the Electronic Numerical Integrator and Computer (ENIAC), the pioneering large-scale electronic computing machine, which was completed in 1947.

ACM and IEEE Computer Society named Luiz André Barroso, Vice President of Engineering at Google, recipient of the 2020 Eckert-Mauchly Award for pioneering the design of warehouse-scale computing and driving it from concept to industry. Today’s datacenters contain hundreds of thousands of servers and millions of disk drives, and make possible the most prevalent applications used by the public today, including cloud computing, powerful search engines, and internet services.

Barroso is widely recognized as the foremost architect of the design of these new ultra-scale datacenters. The cornerstone of his architectural vision was to think of a system holistically, weaving together the individual compute, storage, and networking components into an overall design across large-scale distributed systems.

Barroso has been a thought leader in the field, writing seminal papers and books which reconsidered every aspect of data center and system design. At the same time, he has also guided industry efforts in this area. He was the lead architect of Google’s first custom-built data centers and has been the primary technical leader steering the development of Google’s computing infrastructure for much of the last two decades. This work has been replicated by other large companies. Virtually all the hardware architectures that power today’s internet services and cloud computing systems feature elements introduced by Barroso and his team at Google.

Warehouse-scale computing
Barroso proposed the idea that a datacenter should be designed as a single, massive warehouse-scale computer, popularizing the phrase “the datacenter is the computer.” The workloads of these computers are internet services that run on thousands of CPUs across high-bandwidth networks and require specialized storage systems. Barroso’s designs paired inexpensive hardware with powerful distributed systems software to dramatically change system design. When Barroso’s designs were introduced in the mid-2000s, they garnered a new term: “hyperscale datacenters.” Those designs were attractive not only because they could manage the mushrooming workloads from internet services and cloud computing, but because they also reduced hardware and operating costs. By 2022, the hyperscale datacenter market is expected to grow to more than $80 billion annually.

Hyperscale system architecture
Barroso and his colleagues at Google were the first to abandon traditional server products and work directly with commodity component manufacturers to build low-end servers that were specifically optimized for the efficiency and scalability needs of internet services. In his well-cited IEEE Micro paper, “Web Search for a Planet,” he and his co-authors Jeffrey Dean and Urs Hölzle described the hardware requirements for emerging web services, arguing for designs that used modular hardware coupled with simple robust software. This approach helped dramatically drive down complexity to make systems less expensive to buy and build, easier to maintain, and more adaptable to rapidly-changing workloads.

Energy efficiency
In one of his most influential papers, which has been cited more than 2,300 times, “The Case for Energy-Proportional Computing,” Barroso (with co-author Urs Hölzle) called for a new approach to achieving energy efficiency, where the energy used would be roughly proportional to the utilization of the systems in question. The paper’s key ideas resulted in significant energy efficiencies when computers were operating below peak capacity. It has been documented that standard servers circa 2006 used 70% peak power even when nearly idle, whereas since 2012, after Barroso’s ideas on energy proportionality had been implemented throughout the industry, a standard server consumed only a small fraction of its peak power at idle.

Other key contributions by Barroso include co-leading the Piranha chip project at DEC Western Research. Piranha was ​one of the first multicore processor architectures proposing multiple “wimpy” cores, and many of Piranha’s designs have since been adopted in today’s commercial processors. Barroso’s book, The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines, (co-authored with Urs Hölzle and Parthasarathy Ranganathan) is widely accepted as the authoritative textbook in the field.

Barroso will be formally recognized with the ACM-IEEE CS Eckert-Mauchly Award during the ACM/IEEE International Symposium on Computer Architecture (ISCA), which is being held virtually May 29 – June 3, 2020.

ACM and IEEE Computer Society co-sponsor the Eckert-Mauchly Award, which was initiated in 1979. It recognizes contributions to computer and digital systems architecture and comes with a $5,000 prize. The award was named for John Presper Eckert and John William Mauchly, who collaborated on the design and construction of the Electronic Numerical Integrator and Computer (ENIAC), the pioneering large-scale electronic computing machine, which was completed in 1947.

ACM and IEEE Computer Society named Mark D. Hill, a professor at a professor at the University of Wisconsin—Madison, the recipient of the 2019 Eckert-Mauchly Award. Hill was cited for contributions to the design and evaluation of memory systems and parallel computers. Widely regarded as the leading memory systems researcher in the world today, Hill made seminal contributions to the fields of cache memories, memory consistency models, transactional memory, and simulation. Hill’s work with over 160 co-authors, which has received more than 20,000 citations, has been guided by the tenet that researchers should develop designs and models. The Eckert-Mauchly Award is considered the computer architecture community’s most prestigious award.

In the 1980s Hill developed the “3C” model of cache misses. A “cache miss” is an instance when data requested for processing by software or hardware is not found in the computer’s cache. Cache misses can cause delays as the program or application must then access the data elsewhere. Hill’s 3C model classified these misses into “compulsory misses,” “capacity misses,” and “conflict misses.” The model was influential, as it led to important innovations such as victim caches and stream buffers, and is now a standard concept in computer architecture textbooks.

Many regard Hill’s work in in memory consistency models as his most significant contribution. With his student Sarita Adve, he developed SC for DRF: a consistency model using sequential consistency (SC), where data races can be avoided (data race free, or DRF). Hill’s SC for DRF model has had significant impact for computer architects, especially as multiprocessors became ubiquitous and architects had to reason about which memory consistency model to use in their architectures and implementations. Years after Hill developed SC for DRF, it became the basis of Java and C++ memory models and, more recently, is being used with graphics processing units (GPUs) to understand memory consistency with heterogeneous processors.

Hill’s third major contribution is his work in transactional memory, a technique to minimize blocking due to critical sections. With David Wood he developed the LogTM transactional memory system, one of the first and widely-cited approaches to transactional memory. For the first time, this system enabled transactions to overrun their buffer and cache capacities, making transactions significantly easier for programmers to implement.

Hill (with David Wood and others) also made significant contributions to the evaluation of parallel computers. The Wisconsin Wind Tunnel project, for instance, pioneered fast parallel simulation running on parallel machines. Other important tools Hill has produced to evaluate memory systems and parallel computers include his Dinero cache simulator, as well as the GEMS full system simulator and gem5, which have been cited over 3,000 times by researchers and practitioners. BadgerTrap, one of his most recent tools, studies virtual memory behavior. Hill has also had significant influence on virtual memory implementation. For example, he proposed the idea of “page reservation,” which is now used in Linux.

Hill will be formally recognized with the award at the ACM/IEEE International Symposium on Computer Architecture (ISCA) to be held June 22-26 in Phoenix, Arizona.

ACM and IEEE Computer Society co-sponsor the Eckert-Mauchly Award, which was initiated in 1979. It recognizes contributions to computer and digital systems architecture and comes with a $5,000 prize. The award was named for John Presper Eckert and John William Mauchly, who collaborated on the design and construction of the Electronic Numerical Integrator and Computer (ENIAC), the pioneering large-scale electronic computing machine, which was completed in 1947.

ACM and IEEE Computer Society named Susan Eggers, a professor at the University of Washington’s Paul G. Allen School of Computer Science & Engineering, the recipient of the 2018 Eckert-Mauchly Award. Eggers was cited for outstanding contributions to simultaneous multithreaded processor architectures and multiprocessor sharing and coherency. The Eckert-Mauchly Award is known as the computer architecture community’s most prestigious award.

Widely recognized as one of the leading computer architects in the field, Eggers will be the first woman to receive the Eckert-Mauchly Award in its 39-year history.  She is also atypical among engineers in that she received a BA degree in Economics in 1965 and worked in related fields for 18 years before deciding to switch careers and pursue research in computer engineering. In 1983 she joined the graduate program in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley and began working toward a PhD.  She completed her PhD in 1989, starting her faculty career as assistant professor at the University of Washington at the age of 47.

Eggers’s early work focused on maintaining accurate and efficient cache coherency in shared-memory processors. In computing terminology, a cache refers to a hardware or software component that is used to store frequently-used instructions or data. While cache memory can be retrieved quickly and doesn’t take up much space, problems can arise that can significantly impair data accuracy in shared-memory multiprocessors. For example, in multiprocessor computers, the same data may reside in separate, processor-specific caches. To maintain the uniformity of the data across all processors, however, once one set of data is changed, all copies of the data in other caches throughout the computer system must also change in a timely fashion—otherwise data could potentially be lost or overwritten. This management of data is called cache coherency. Beginning in the late 1980s, Eggers made significant contributions to cache coherency protocols as well as other memory-related challenges in multiprocessor computers. She performed the first data-driven study of data sharing in shared-memory multiprocessors which greatly enhanced the field’s understanding of both hardware and software coherency techniques.

Eggers is best known for her foundational work in developing and helping to commercialize simultaneous multithreaded (SMT) processors, one of the most important advancements in computer architecture in the past 30 years. In the mid-1990s, Moore’s Law was in full swing and, while computer engineers were finding ways to fit up to 1 billion transistors on a computer chip, the increase in logic and memory alone did not result in significant performance gains. Eggers was among those who argued that increasing parallelism, or a computer’s ability to perform many calculations or processes concurrently, was the best way to realize performance gains.

From 1995 through 2003, she and her colleagues at the University of Washington developed and validated the idea of SMT as a way to increase central processing unit (CPU) performance. SMT is a technique that permits multiple independent sequences of programmed instructions (threads) to better utilize a computer’s resources by converting their thread parallelism to a simpler instruction-level parallelism. Eggers and her colleagues at the University of Washington presented several landmark papers at the International Symposium of Computer Architecture (ISCA) and other leading gatherings that demonstrated the underlying concepts, performance benefits and implementation simplicity of SMT.

Today, SMT architecture as developed by Eggers and her colleagues remains an essential component in the processors of commercial manufacturers, including Intel and IBM. Earlier in her career, she initiated technology transfer of SMT to product teams at IBM, Fujitsu, MemoryLogix and Sun Microsystems.

Eggers will be formally recognized with the award at the ACM/IEEE International Symposium on Computer Architecture (ISCA) to be held June 2-6 in Los Angeles.

ACM and IEEE Computer Society co-sponsor the Eckert-Mauchly Award, which was initiated in 1979. It recognizes contributions to computer and digital systems architecture and comes with a $5,000 prize. The award was named for John Presper Eckert and John William Mauchly, who collaborated on the design and construction of the Electronic Numerical Integrator and Computer (ENIAC), the pioneering large-scale electronic computing machine, which was completed in 1947.

Widely recognized as one of the leading computer architects in the field, Susan Eggers, a professor at the University of Washington’s Paul G. Allen School of Computer Science & Engineering, was the first woman to receive the Eckert-Mauchly Award in its 39-year history. She is also atypical among engineers in that she received a BA degree in Economics in 1965 and worked in related fields for 18 years before deciding to switch careers and pursue research in computer engineering. In 1983 she joined the graduate program in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley and began working toward a PhD. She completed her PhD in 1989, starting her faculty career as assistant professor at the University of Washington at the age of 47.

The late Charles P. “Chuck” Thacker was named recipient of the ACM - IEEE CS Eckert-Mauchly Award for fundamental networking and distributed computing contributions including Ethernet, the Xerox Alto, and development of the first tablet computers. Often hailed as an “engineer’s engineer,” Thacker made fundamental contributions across the full breadth of computer development, from analog circuit and power supply design to logic design, processor and network architecture, system software, languages, and applications.

In 1970, Xerox opened its Palo Alto Research Center (PARC) and hired several leading computer scientists and engineers, including Thacker. Early on, the staff at Xerox PARC was using a time-sharing approach in which various terminals were connected to a single computer. Because time sharing was a slow and cumbersome process, leaders at Xerox PARC conceived the idea of developing personal computers as part of a network that would be used for communication as well as computation.

Mainframe computers in the early 1970s were so large that they took up whole rooms, and their expense made them relatively scarce. Under the paradigm at the time, computer architecture needed to be either scaled up (more hardware) for better performance, or scaled down (less hardware) for lower cost. Thacker realized that a personal computer would need to be designed differently from a standard computer to address space constraints, maintain strong performance, and be inexpensive if it was to become pervasive.

At the same time, the idea of a “personal” computer that would be geared more toward human-paced activities called for the engineers to prioritize input/output (I/O) functions rather than application functions, as had traditionally been the case.

The new design feature Thacker employed as the Lead Engineer in what would become the Xerox Alto Computer was a central processing unit (CPU) microprocessor that used microcode for most of the computer’s I/O functions, rather than hardware. The microcode controlled various tasks, including executing the normal instruction set, memory refresh, and network and display functions. The Xerox Alto was therefore not simply a mini-version of existing computers, but had a novel architecture that allowed it to deploy new kinds of software.

Today the Alto is recognized as being the first modern personal computer. The initial architecture of the Alto gave rise to other important inventions developed by engineers at Xerox PARC including WYSIWIG (What You See Is What You Get) editing, laser printing, drawing and painting, email, mouse-driven graphical user interfaces, and many other features that are commonplace in personal computers today.

Another critical innovation of Thacker’s that was an outgrowth of his work on the Alto was the development of hardware for Bob Metcalfe’s invention of the Ethernet Local Area Network (LAN), which facilitated communication among computers.

Twenty years after the development of the Xerox Alto, Thacker made another foundational contribution to personal computing with the development of the Lectrice, a laboratory prototype for today’s portable PCs. He went on to develop a prototype upon which Microsoft Tablet PC software was developed, as well as a system for reading electronic books that laid the groundwork for many of today’s e-readers. One of Thacker’s most recent contributions is the design of AN3, a low-cost, efficient circuit-switched data center network.

Uri Weiser did pioneering industry and academic work in high performance processors and multimedia architectures. In a nearly 40-year career that has included roles in government, industry and academia, Weiser has made seminal contributions, including defining the first Intel Pentium processor architecture and being a recognized leader in asymmetric and heterogeneous manycore architecture.

In the late 1980s, Weiser was an engineer with Intel’s Design Architecture Group. At the time, Intel was using a Complex Instruction Set Computer (CISC) design for its X86 microprocessors. A debate emerged within the computing field as to whether Reduced Instruction Set Computer (RISC) design would eclipse the CISC design. Intel was contemplating whether to continue to manufacture its X86 processors using the CISC design or abandon the program and repurpose the company to design its microprocessors using RISC-based architecture.

Weiser single-handedly convinced Intel executives to continue with the CISC-based X86 processors by showing that through adding new features such as superscalar execution, branch predication and more, the X86 processors could perform competitively against the RISC family of processors. Wieser’s architectural enhancements laid the foundation for the Intel Pentium processor.

The ACM/IEEE CS Eckert-Mauchly Award is known as the computer architecture community’s most prestigious award. Weiser will receive the 2016 Eckert-Mauchly Award at the ACM/IEEE International Symposium on Computer Architecture (ISCA) to be held June 18 to 22 in Seoul, Korea.

Uri Weiser is currently an emeritus professor in the Electrical Engineering department of the Technion ̶ Israel Institute of Technology (IIT). He holds 13 patents and has authored over 50 publications. He was recognized with the Intel Achievement Award on two occasions. Additionally, he has been named an Intel Fellow, a Fellow of IEEE and an ACM Fellow. Weiser is active on the advisory boards of numerous startups.

ACM and IEEE Computer Society jointly presented the 2015 Eckert-Mauchly Award to Norman Jouppi for pioneering contributions to the design and analysis of high-performance processors and memory systems. With a distinguished career spanning over 35 years, including many notable contributions to the computer architecture field, his major technical contributions can be classified into three broad areas: Memory Hierarchy, Heterogeneous Architectures, and CACTI tools.

Dr. Jouppi has made innumerable contributions to memory hierarchy design, with the most significant multiple ideas presented in his 1990 ISCA paper “Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers”. This paper introduced two major concepts: the victim buffer and prefetching stream buffer, and have been widely adopted by industry with numerous machines containing victim caches and virtually all machines incorporating prefetching stream buffers, which are evolutions of Dr. Jouppi’s original ideas.

As the world moved to homogenous multi-core processors, Dr. Jouppi also introduced the radical notion of single-ISA heterogeneous architectures, which was a key step in the notion that specialization can provide better efficiency than homogeneous architectures, while preserving general-purpose programmability. This idea has also been adopted by industry in the form of ARM’s big.LITTLE design that combines multiple out-of-order processors with multiple in-order processors and Nvidia's Tegra 3 and 4, which feature multiple big cores and a single very energy efficient small core.

Dr. Jouppi has made a huge impact influencing and facilitating computer architecture research through the introduction of the CACTI tools. These tools, initially used for evaluating area and timing tradeoffs for SRAM storage structures, have been extensively used in the community. CACTI later added power modeling and other specializations such as DRAM, stacked DRAM and non-volatile storage that enhanced its utility. In addition to its standalone usage, CACTI has also been a fundamental component of many subsequent tools, such as McPAT, Wattch and GPUWattch. CACTI has had a major impact on the community, facilitating analyzes that not only showed the performance gains of ideas, but also the power and area and practicality of those ideas.

Dr. Jouppi, currently a Distinguished Hardware Engineer for Google, is recognized for his vast technical contributions, his major impact on research directions and industrial design, as well as for his broad influence from leadership roles in several influential processor designs, and directing research teams at Digital, Compaq and Hewlett-Packard.